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U2785B
DECT PLL / TX IC
Description
The U2785B is an RF IC for low-power DECT transmit applications. The SSO28-packaged IC is a complete PLL including a 1-GHz prescaler, on-chip frequency doubler, biasing for off-chip VCO, an integrated TX-filter and a modulation compensation circuit for advanced closedloop modulation concept. No mechanical tuning is necessary in production. Electrostatic sensitive device. Observe precautions for handling.
Features
D 1-GHz PLL, TX data filter (10.368-MHz / 20.736-MHz reference clock), frequency doubler D Low current consumption D Few external components D Supply-voltage range 2.7 V to 4.7 V D Switchable charge-pump current for enhanced switching time D Two operational amplifiers for active loop filter D Advanced closed-loop modulation (with 10.368-MHz / 20.736-MHz reference clock) and open-loop modulation supported
Block Diagram
FD_OUT1 FD_OUT2 CP REF_CLK
FD
RF_IN
CP 2f f
RC Bandgap n
TX_DATA
f
PU OLE
Control logic
PC f n
PD
MCC
GF
GF_DATA LD
OP 1 DAC + - + -
OP 2 3-wire bus
DAC OP_REF_P
OP1_N
OP1_OUT
OP2_N
OP2_OUT CLOCK DATA ENABLE 14638
Figure 1. Block diagram
Ordering Information
Extended Type Number U2785B-MFS U2785B-MFSG3 SSO28 SSO28 Package Tube Taped and reeled Remarks
Rev. A5, 18-Aug-00
1 (15)
Preliminary Information
U2785B
Pin Description
A A A AAAAAAAAAA AAAAAA AAAAAAAAA AAAAAA A A AAAAAAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA AAAAAAA A AAAAAAAAAA AAAAAA A A AAAAAAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA AAAAAAA A AAAAAAAAAA AAAAAA A A AAAAAAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA AAAAAAA A AAAAAAAAAA AAAAAA A A AAAAAAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA AAAAAAA A AAAAAAAAAA AAAAAA A A A A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA AAAAAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA AAAAAAA A AAAAAAAAAA AAAAAA AAAAAA A AAAAAAAAAA A AAAAAAAAAA AAAAAA A AA A A A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA AAAAAAAAAA AAAAAAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA AAAAAAAAA AAAAA A AAAAAAAAAA A AA A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAAA AAAAAAA A
1 2 3 4 5 6 7 8 9 CLOCK DATA 3-wire bus: clock input 3-wire bus: data input ENABLE LD 3-wire bus: enable input Lock-detect output REF_CLK I_CP_SW Reference frequency input Charge-pump current switch Frequency doubler buffer ground Frequency doubler buffer output Supply voltage GND_FD_ OUT FD_OUT1 FD_OUT2 VS 10 11 GF_DATA GND_CP VS_CP CP Modulation output (Gaussian-filtered data signal) Charge-pump ground Charge-pump output Charge-pump supply voltage 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 OP1_N Operational amplifier 1 inverting input Operational amplifier reference voltage (internal) OP_REF_P OP1_OUT GND_OP OP2_N Operational amplifier 1 output Operational amplifier ground Operational amplifier 2 inverting input Operational amplifier 2 output VCO bias voltage output OP2_OUT VCO_BIAS GND_RF_IN RF input ground RF_IN DAC OLE PU RF input from VCO to doubler and PLL DAC for VCO pretune Digital ground GND_D Open-loop enable input Power-up input (active high) TX_DATA Digital TX data input to Gaussian filter and modulationcompensation circuit 2 (15)
Pin
Symbol
Function
CLOCK DATA ENABLE REF_CLK LD I_CP_SW
1 2 3 4 5 6
28 TX_DATA 27 PU 26 OLE 25 GND_D 24 DAC 23 RF_IN 22 GND_RF_IN
GND_FD_OUT 7 FD_OUT1 FD_OUT2 VS GF_DATA GND_CP VS_CP CP 8 9 10 11 12 13 14 Figure 2. Pinning
U2785B
21 VCO_BIAS 20 OP2_OUT 19 OP2_N 18 GND_OP 17 OP1_OUT 16 OP_REF_P 15 OP1_N
Rev. A5, 18-Aug-00
Preliminary Information
U2785B
Functional Blocks
CP DAC FD GF OP1 OP2 Charge pump D/A converter for pretuning the VCO Frequency doubler Gaussian filter for transmit data 1st amplifier for loop filter 2nd amplifier for loop filter MCC PC PD RC VCO Modulation-compensation circuit Programmable counter = main counter (MC) + swallow counter (SC) Phase detector Reference counter Voltage-controlled oscillator
Absolute Maximum Ratings
All voltages refer to GND (Pins 7, 12, 18, 22 and 25) Parameter Supply voltage Logic input voltage Junction temperature Storage temperature Pins 10, 13 Pins 1, 2, 3, 6, 26, 27 and 28 Symbol VS VIN Tj Tstg Value 5.0 -0.3 to VS 150 -40 to +150 Unit V V C C
Thermal Resistance
Parameter Junction ambient Symbol RthJA Value 130 Unit K/W
Operating Range
All voltages refer to GND (Pins 7, 12, 18, 22 and 25) Parameter Supply voltage Ambient temperature Symbol VS Tamb Min. 2.7 -25 Typ. 3.0 +25 Max. 4.7 +85 Unit V C
AAAA A A A A A AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AA A A A A
Rev. A5, 18-Aug-00 3 (15)
Preliminary Information
AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A A AAA A A A AA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A AAA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A AA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A AA A AA A AAA A A A AA A A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A AAA A A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA AA A AAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A AA A AAAAAA AAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAA AAA A AA AA AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAA AAA AA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAA AAAA AAAAAAAAAA AAAAAAAA A AA A A AAA A A A AA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AA AAAA AAAAAAAAAAAAAAAAA A A A A AA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAA A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A A A AA AAAAAAAAA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Test conditions (unless otherwise specified) : VS = 3 V, Tamb = 25C
Electrical Characteristics
U2785B
4 (15) External reference input voltage External reference input frequency Scaling factor reference counter Scaling factor swallow counter Scaling factor main counter Scaling factor prescaler Input voltage Input frequency PLL Subharmonic suppression Harmonic suppression Output power Frequency doubler Supply current CP Supply current pp y Power supply Parameter AC-coupled sine wave Pin 4 AC-coupled sine wave Pin 4 fRF_IN = 800 to 1000 MHz AC-coupled sine wave Pin 23 PRF_IN = -10 dBm, Pin 8 and 9 (differential) PRF_IN = -10 dBm, 2nd and 3rd, Pin 8 and 9 (differential) PRF_IN = -10 dBm, Zload = 50 W (differential), Pins 8 and 9 (differential) VVS_CP = 3 V, PLL in lock condition, Pin 14 TX, MCC, GF, OP, FD ON TX, MCC, GF, OP ON TX, MCC, GF ON TX, MCC ON TX (OLE = `0`) RX (OLE = `1`) VPU = low level = `0` fRF_IN = 900 MHz Test Conditions / Pins Pin 10 Pin 4 Pin 23 VREF_CLK fREF_CLK PFD_OUT Symbol VRF_IN fRF_IN IS,OFF SPSC SHS SMC SRC SSC ICP HS IS IS IS IS IS IS Min. - 20 - 20 - 10 800 50 20 5 - 0 - - 10.368 20.736 12/16/ 24 31/32/ 33/34 32/33 Typ. -5 5.6 30 19 17 15 13 1 1
Preliminary Information
Rev. A5, 18-Aug-00 Max. 1000 250 200 -3 22 31 10 - - - mVrms mVrms MHz MHz dBm Unit dBc dBc mA mA mA mA mA mA A A
AAA A A A AA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAA AA AA AAAA AAAAAAAAA A A A AA AAAA A A A AA A AAA AAA AA AA AAAA AAAAAAAAA AAAAAAAA A A A A AA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A AA A AA A AAA A A A AA A A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A AA A A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A A A AA A A AAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AA AAAA AAAAAAAAAAAAAAAAA AAA A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAA A A AAAAAAAAAAA AAAAAAAA AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAA AAAA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A AAA A A A AA A AAA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAA AAA AA AA AAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA AAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAA AAAAA AAAAAAAAA AAAAAAAA A AA AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A AAA A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A AA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAA AAAA AAAAAAAAA AAAAAAAAA A AA A A AAA AAA AA AA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Test conditions (unless otherwise specified) : VS = 3 V, Tamb = 25C
Rev. A5, 18-Aug-00
Electrical Characteristics (continued)
Temperature coefficient
Bias voltage g
VCO biasing
Current scaling factor
Maximum output current
TX data filter clock
Gaussian transmit filter (Gaussian shape B
Current scaling factor
Integration counter
Oversampling
Modulation-compensation circuit @ max. DSV 64
Common-mode input voltage
Output-voltage range
Open-loop gain
Input offset voltage
Excess phase
Power gain bandwidth
Operational amplifiers 1 and 2
Leakage current
Current scaling factor
Output current
Charge pump, active when RX, TX
Parameter
Pin 21
Standby, PU = '0`
See bus protocol D6 ... D8 IGF_DATA = GFCS IGF_NOM Pin 11
Polarity see bus protocol D13, GFCS = 100%, Pin 11
fREF_CLK = 20.736 MHz, TX, 18 taps in filter, SRC = 24
fREF_CLK = 10.368 MHz, TX, 18 taps in filter, SRC = 12
See bus protocol E3 ... E5
fREF_CLK = 10.368 MHz or fREF_CLK = 20.736 MHz
Rload = 1 kW, Cload = 15 pF Pins 17 and 20
See bus protocol D0...D2 ICP = CPCS ICP_NOM
CPCS = 100%, VI_CP_SW = '1`, VCP = VVS_CP / 2
CPCS = 100%, VI_CP_SW = '0`, VCP = VVS_CP / 2
Preliminary Information
Test Conditions / Pins Pin 14 Pins 15, 16 and 19 Pins 17 and 20 Pins 17 and 20 Pins 15, 16 and 19 Pins 17 and 20 T = 0.5) fREF_CLK has to be chosen
ICP_NOM5 ICP_NOM1
|IGF_NOM|
fTXFCLK
fTXFCLK
VVCO_O
Symbol
TCVCO
PGBW
MCCS
GFCS
CPCS
VVCO
MAC
ICP_O
OVS
Voffs
Vout
Vin
g
- 576
Min.
0.3
0.3
60
60
60
-
-
-
10.368
10.368
100AAAA pA
- 3.3
Typ.
"5
"1
1
1.5
80
70
80
10
9
U2785B
VS - 0.3
VS - 0.3
Max.
130
130
576
130
10
-
-
-
degree
mV/K
MHz
MHz
MHz
Unit
5 (15) mV mV mA mA A dB % % % V V V
AAA A A A AA A A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A AAA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A AA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A AAA A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A A A AA A AAA A A A AA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAA AAA AA AA AAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAA AAA AA AA AAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A A A AA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AA AAAA AAAAAAAAAAAAAAAAA AAA A A A AA A A A A AA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAA A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAA A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A A A AA A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A A A AA AAAAAAAAA AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAA AAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Test conditions (unless otherwise specified) : VS = 3 V, Tamb = 25C
Electrical Characteristics (continued)
U2785B
6 (15) Settling time Switched from active operation-> standby PU = '1` to standby Settling time Switched from standby to PU = '1` standby-> active operation Settling time VS = 0 -> active operation Power-up low input current Power-up high input current Power-up low input level Power-up high input level Standby control Low input current High input current Low input level High input level Logic input levels (CLOCK, DATA, ENABLE, I_CP_SW, OLE, GF_DATA) Clock 3-wire bus Saturation voltage Leakage current Test-mode output Lock-detect output Lock-detect and test-mode output Output impedance DAC high level DAC step level DAC low level DAC for VCO pretune, 3-bit programming, see bus protocol D3 ... D5 Parameter Switched from VS = 0 to VS = 3 V VPU = 0 V, PU = '0` VPU = 0.5 V VPU = 3 V, PU = '1` VPU = 4.5 V PU = '0` (standby) PU = '1` = '0` = '1` = '0` = '1` IOL = 0.5 mA VOH = 4.5 V Test modes see bus protocol E0 ... E2 Locked = '1`, unlocked = '0` Iload = 1 A Iload = 1 A Iload = 1 A Test Conditions / Pins Pin 1 Pin 5 Pin 27 VDAC_max RDAC_out VDAC_step VDAC_min
VLD_min
Preliminary Information
Symbol VPU_O ILD_O IPU_O fclock VPU ViH tsoa IPU ViL LD LD tsas tssa IiH IiL Pin 24 Min. 100 220 2.0 1.5 -5 -5 - - Pins 1, 2, 3, 6, 26 and 28 1.152 Typ. 125 300 2.3 0.3 0.3 10 - - Rev. A5, 18-Aug-00 Max. 150 420 0.1 1 0.7 0.5 0.4 10 10 5 5 5 - - 2 MHz Unit A A A kW A A s s s V V V V V V V V
U2785B
PLL Principle
RF_IN Programmable counter PC: (main counter MC + swallow counter SC)
fLO = fRC (SMC 32 + SSC)
fLO
fPC Phase frequency detector PD ICP Loop filter VCO Frequency doubler FD 2 fLO
FD_OUT
fRC = 0.864 MHz
DAC
GF_DATA
Controlled phase shifting
Modulation compensation MCC
Gaussian filter GF
Reference counter RC REF_CLK 10.368 MHz 13.824 MHz* 20.736 MHz SRC 12 16 24 10.368 MHz
* MCC and GF not possible
1.152 Mbit/s
PLL reference frequency REF_CLK
TX_DATA
Baseband controller
14639
Figure 3. PLL principle
Rev. A5, 18-Aug-00
7 (15)
Preliminary Information
AAAAA A A A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA AA A A A A A AA A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAA AAAA A A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAA A A A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAA AAAA A A A A AA A AAAAA A A A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAA AAAA A A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAA A A A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAA AAAA A AAAAA AAAAAAA AAAA A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAA A A A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA A A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA AA A A A A A AA A A AA A AAAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAA AAAA AAAAA AAAA AAAAAAA AAAA A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAA A A A A A AA A AAAAA A AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAA AAAA A A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAA AAAA A A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AA A A A AA A AAAAAAAA AAAA AAAA AAAA AAAAAAA AAAA AAAA AAAA AAAA AAAA AAAAAAA AAAA A A A A AA A
The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for an optional DECT band extension. Intermediate frequencies of 110.592 and 112.32 MHz are supported. Limits
U2785B
8 (15) TX RX Mode TX RX RX TX Mode 110.952 112.32 110.592 112.32 112.32 110.592 fIF (MHz) fIF (MHz) Channel CO C1 C2 C3 C4 C5 C6 C7 C8 C9 CO C1 C2 C3 C4 C5 C6 C7 C8 C9 CO C1 C2 C3 C4 C5 C6 C7 C8 C9 fmax fmin fANT (MHz) 1714.176 1824.768 1826.496 1933.632 2044.224 2045.952 fANT (MHz) fLO (MHz) 2fLO (MHz) 1897.344 948.672 1897.344 1895.616 947.808 1895.616 1893.888 946.944 1893.888 1892.16 946.08 1892.16 1890.432 945.216 1890.432 1888.704 944.352 1888.704 1886.976 943.488 1886.976 1885.248 942.624 1885.248 1883.52 941.76 1883.52 1881.792 940.896 1881.792 1897.344 893.376 1786.752 1895.616 892.512 1785.024 1893.888 891.648 1783.296 1892.16 890.784 1781.568 1890.432 889.92 1779.84 1888.704 889.056 1778.112 1886.976 888.192 1776.384 1885.248 887.328 1774.656 1883.52 886.464 1772.928 1881.792 885.6 1771.2 1897.344 892.512 1785.024 1895.616 891.648 1783.296 1893.888 890.784 1781.568 1892.16 889.92 1779.84 1890.432 889.056 1778.112 1888.704 888.192 1776.384 1886.976AAAAA 1774.656 887.328 1885.248 886.464 1772.928 1883.52 885.6 1771.2 1881.792 884.792 1769.472 fLO (MHz) 857.088 857.088 857.088 966.816 966.816 966.816 2fLO (MHz) 1714.176 1714.176 1714.176 1933.623 1933.623 1933.623
Preliminary Information
SMC 31 31 31 34 34 34 SMC 34 34 34 34 34 34 34 34 34 34 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Rev. A5, 18-Aug-00 SSC 0 0 0 31 31 31 SSC 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 1 0
U2785B
Formulas fANT C1 - fANT C2 = 1.728 MHz for TX: fLO = fANT / 2 for RX: fLO = (fANT - fIF) / 2 SMC = integer (fFD / 0.864 MHz / 32) SSC = MOD ((fFD / 0.864 MHz) / 32)
Serial Programming Bus
Reference and programmable counters can be programmed by the 3-wire bus (CLOCK, DATA and ENABLE). Besides this information, additional control bits as phase-detector polarity and scaling of charge-pump currents as well as internal currents for Gaussian lowpass filter and modulation-compensation circuit can be transferred. After setting the enable signal to low condition, the data status is transferred bit-by-bit on the rising edge of the clock signal into the shift register, starting with the MSB bit. When the enable signal has returned to high condition, the programmed information is loaded into the addressed latches according to the address-bit condition (last bit). Additional leading bits are ignored and there is no check carried out how many pulses arrived during enable low condition. The bus then returns to low-current standby mode until the enable signal changes to low again. During standby of the PLL, the information in the registers of the PLL is not maintained.
Control Signals
I_CP_SW LD input for switching charge-pump current by factor 5 output which is active after PLL is locked and test-mode output (according to programmed test mode) enable input for open-loop modulation DAC for VCO band switch hardware power-up / standby of complete PLL / TX IC
OLE DAC PU
Bus Protocol Formats
MSB Data bits D22 0 D21 1 D20 0 D19 1 D18 SC 0 1 0 1 D17 D16 D15 D14 1 D13 0 D12 PS 0 0 D11 D10 GF 1 D9 MCC 1 1 D8 D7 GFCS 0 FD 0 OP 1 1 1 D6 D5 D4 DAC 1 MCCS 0 0 0 1 1 D3 D2 D1 CPCS 0 TEST 0 0 0 D0 LSB Address bit A0 1 1 0 0
RC
MC
Standard bit setting:
word 1 word 2
1
PLL Settings
RC (Reference Divider) D22 0 0 1 1 D21 0 1 0 1 SCR - 12 16 24 0 0 1 1 MC (Main Divider) D15 D14 0 1 0 1 SMC 31 32 33 34 D20 0 0 0 0 1 1 1) D19 0 0 0 0 1 1 SC (Swallow Counter) D18 0 0 0 0 1 1 D17 0 0 1 1 1 1 D16 0 1 0 1 0 1 SSC 1) 0 1 2 3 30 31
SPGD = 32
SMC + SSC
SSC = [D16]
20 + [D17]
21 + .... + [D20]
24
Rev. A5, 18-Aug-00
9 (15)
Preliminary Information
U2785B
Phase Settings
Phase of GF_DATA D13 0 1 GF_DATA Source Sink Phase of MCC Internal Connection D12 1 0 MCC_DATA Normal Inverted D11 1 0 Phase of CP (Charge Pump) fR > fP ISource ISink fR < fP ISink ISource fR = fP High imp. High imp
Current-Saving Power-up/ down Settings
D10 0 1 GF (Gaussian Filter) off on D9 0 1 MCC (ModulationCompensation Circuit) off on E7 0 1 FD (Frequency Doubler) off on E6 0 1 OP1 + OP2 (Op Amps) off on
Current Gain Settings
GFCS (Gaussian-Filter Current Settings) D7 D6 GFCS 0 0 60% 0 1 70% 1 0 80% 1 0 0 1 1 1 0 1 0 1 90% 100% 110% 120% 130% CPCS (Charge-Pump Current Settings) D1 D0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 0 1
D8 0 0 0 0 1 1 1 1
D2 0 0 0 0 1 1 1 1
CPCS 60% 70% 80% 90% 100% 110% 120% 130%
MCCS (Modulation-Compensation Current Settings) E5 E4 E3 MCCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130%
Pretune DAC Voltage Settings
Pretune DAC Voltage D4 D3 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1
Test Mode Settings
Test Output Pin LD (Lock Detect) E0 Signal at Lock Detect Output 0 Lock detect 1 RC out 0 PC out 1 RC out div. by 2048 (MCCTEST) 0 CP tristate only 1 RC out 0 PC out 1 RC out div. by 2 (GFTEST)
D5 0 0 0 0 1 1 1 1
DAC 0.3 V 0.6 V 0.9 V 1.2 V 1.4 V 1.7 V 2.0 V 2.3 V
D11 x 0 1 x x 0 1 x
E2 0 0 0 0 1 1 1 1
E1 0 0 1 1 0 0 1 1
CP Mode Active Active Active Active High impedance High impedance High impedance High impedance
10 (15)
Rev. A5, 18-Aug-00
Preliminary Information
U2785B
3-Wire Bus Protocol
DATA CLOCK ENABLE
TL TS TC TH TEC TED TT
14641
MSB
LSB
Figure 4. 3-wire bus protocol timing diagram
Parameters Set time data to clock Hold time data to clock Clock pulse width Set time enable to clock Hold time enable to clock Hold time enable to data Time between two protocols
Symbol TS TH TC TL TEC TED TT
Min. Value 434 0 434 217 0 0 868
Unit ns ns ns ns ns ns ns
Typical Application Circuit
VCO
OLE PU TX_DATA
Loop filter LF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Control logic
PC
DAC
PD OP2 OP1
f n
MCC
PLL/TX U2785B
n f 3 4
3-wire bus 1
CLOCK DATA ENABLE REF_CLK LD I_CP_SW
RC
FD
f 2f 8
GF
Bandgap 10 11 12
CP
2
5
6
7
9
13
14
VS FD_OUT1 FD_OUT2
14642
Figure 5. Typical application circuit
Rev. A5, 18-Aug-00
11 (15)
Preliminary Information
U2785B
Input / Output Interface Circuits
VS VS
10k 1, 2, 3, 6, 26, 28 5k (10k) 5k (10k) 4 REF_CLK
10k
14643
14644
Figure 6.
Figure 9.
VS
5 LD 100 8, 9 FD_OUT1 FD_OUT2
14645
7 GND_FD_OUT
14646
Figure 7.
Figure 10.
13 VS VS_CP
11 GF_DATA
14 CP
12
14647
GND_CP
14648
Figure 8.
Figure 11.
12 (15)
Rev. A5, 18-Aug-00
Preliminary Information
U2785B
Input / Output Interface Circuits (continued)
VS VS
1k 15, 19 OP1_N OP2_N 16 OP_REF_P 21 VCO_BIAS
18 GND_OP
14649 14652
Figure 12.
VS
Figure 15.
VS
AB- control
17, 20 OP1_OUT OP2_OUT 10k 18 GND_OP
14651
24 DAC
14654
Figure 13.
VS
Figure 16.
20k
10k 10k
140k
1.5k 23 RF_IN
1.5k
27 PU
10k
25k
25k
22
14655
GND_RF_IN
14653
Figure 14.
Figure 17.
Rev. A5, 18-Aug-00
13 (15)
Preliminary Information
U2785B
Input / Output Interface Circuits (continued)
VS 10 VS_CP 13 GND_FD_OUT 7 GND_CP 12 GND_OP 18 GND_RF_IN 22 GND_D 25
14656
Figure 18.
Package Information
Package SSO28
Dimensions in mm
9.10 9.01 5.7 5.3 4.5 4.3
1.30 0.25 0.65 8.45 28 15 0.15 0.05 6.6 6.3 0.15
technical drawings according to DIN specifications
13018
1
14
14 (15)
Rev. A5, 18-Aug-00
Preliminary Information
U2785B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
2.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev. A5, 18-Aug-00
15 (15)
Preliminary Information

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